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Multimedia ICs
Audio digital delay (KARAOKE echo)
BU9252S / BU9252F
The BU9252S and BU9252F are digital delays specifically for Karaoke systems. Each has an internal sample hold circuit, an 8-bit A / D and D / A converter and 2kB SRAM, and allows for the selection of one of eight delay times just by attaching an inexpensive ceramic resonator. A digital echo system can be formed by using either of these ICs together with the BA7725S or BA7725FS.
*Applications system Karaoke echo
Electronic circuits that require signal delays
*Featuresdigital delay circuit. 1) Internal
2) Internal 8-bit A / D converter. Sample rate. (14.22kHz when fOSC = 455kHz). 3) Internal 2k bytes data SRAM.
4) Internal 8-bit D / A converter. 5) CMOS design for low power consumption. 6) Internal sample hold circuit. 7) Internal feedback resistors and capacitors for oscillator circuits.
*Block diagram
18 VDD 17 16 15 14 13 12 11 10 GND 9 OSCO TDO0 TDO1 OSCI DCNT2 8 TST0 TST1 TST2 TDIN
TEST CIRCUIT 8 x 2k SRAM
8bit A/D
8bit D/A
ADDRESS COUNTER AND MAIN TIMING
1
2
S/H
3
4
5
6
DCNT0
DCNT1
S/H
AGND
AIN
AVDD
AOUT
7
1
Multimedia ICs
BU9252S / BU9252F
*Pin descriptions
Pin No. 1 2 3 4 5 6 7 8 9 Pin name S/H AIN AGND AOUT AVDD DCNT0 DCNT1 DCNT2 GND Function For attaching sample-and-hold capacitor Analog input Analog circuit ground Analog output Analog circuit power supply Delay setting input Delay setting input Delay setting input Digital circuit ground Pin No. 10 11 12 13 14 15 16 17 18 Pin name OSCO OSCI TDO1 TDO0 TDIN TST2 TST1 TST0 VDD Function Oscillator pin 2 Oscillator pin 1 Test pin (output) Test pin (output) Test pin (input) Test mode setting Test mode setting Test mode setting Digital circuit power supply
2
Multimedia ICs
BU9252S / BU9252F
*Input / output circuits
Pin name Pin No. Internal equivalent circuit Pin name Pin No. Internal equivalent circuit
S/H
1
OSCI AIN 2 OSCO
11 10
TDIN DCNT0 DCNT1 DCNT2
14 6 7 8
TDO0 TDO1
13 12
+
AOUT
4
D/A
-
TST0 TST1 TST2
17 16 15
Built-in 0.875x amplifier as output buffer.
3
Multimedia ICs
BU9252S / BU9252F
*Absolute maximum ratings (Ta = 25C)
Parameter Power supply voltage Power dissipation BU9252S BU9252F Symbol VDD Pd Tstg VIN VOUT Limits - 0.3 ~ + 7.0 6001 4502 - 55 ~ + 125 - 0.3 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 Unit V mW C V V
Storage temperature Input voltage Output voltage
1 IC only. Reduce by - 6mW / C for each in Ta of 1C over 25C. 2 IC only. Reduce by - 4.5mW / C for each in Ta of 1C over 25C.
*Recommended operating conditions
Parameter Power supply voltage Analog power supply voltage Input "L" voltage Input "H" voltage Analog input voltage Clock frequency Operating temperature Symbol VDD AVDD VIL VIH VAIN fOSC Topr Limits 4.5 ~ 5.5 VDD 0.0 ~ 0.2VDD 0.8VDD ~ VDD 0 ~ AVDD 200 ~ 1000 - 10 ~ + 70 Unit V V V V V kHz C
*Electrical characteristics (unless otherwise noted, Ta = 25C, VDD = AVDD = 5V)
Parameter Supply current Analog output current Analog input impedance A / D to D / A precision OSCO output "L" voltage OSCO output "H" voltage OSCI feedback loop current Oscillation capacity Symbol IDD IAOUT RAIN RES VLOSC VHOSC IOSCI -- Min. -- 1 0.3 12 -- -- 3.8 1 -- Typ. 3.5 4 0.8 25 2 0.6 4.4 6 150 Max. 12 -- -- 60 -- 1.2 -- 20 -- Unit mA mA mA k LSB V V A pF IOL = 100A IOH = - 100A VOSCI = VDD Conditions VAIN = AVDD, fOSC = 455kHz VAOUT = 1V, VAIN = 0V VAOUT = 0.5VDD, VAIN = VDD
The bias circuit is impedance.
4
Multimedia ICs
BU9252S / BU9252F
*Circuit operation for signal input pin (1) External capacitor
Audio signals compressed by the BA7725S or BA7725FS have their DC component removed by an AC coupling capacitor and are then input to pin 2 of BU9252S or BU9252F. At this stage, level deviations occur because the input signal is capacitor-divided by this AC coupling capacitor C28 and by sampling hold capacitor C27 connected to pin 1. To prevent this, make sure that C27 is much lower than C28.
(Note: The numbers of external components are the numbers used in the system application example.)
C27 1
(3) Delay timer settings The delay time (i.e., the length of time the signal is stored in the SRAM) can be set to any of eight settings between the maximum and minimum delay times by setting pins 6, 7 and 8 to the combination of logic signal inputs that results in the corresponding number of counts. The maximum and minimum delay times are determined by the oscillation frequency of the attached ceramic resonator.
(dB)
C28 2 S/H (t)
C
C
C
The sample-held analog signal is converted to digital by the serial 8-bit A / D converter and then temporarily stored in the internal SRAM (2k bytes). (2) Relationship between oscillation frequency (CLK) and delay time Sample rate F = fOSC / 32 (fosc: oscillation frequency) F = 14.22kHz at fosc = 455kHz Sample period T = 1 / F Delay time Dtime = T x number of counts
C : Delay time (ms)
The delay time can be set to any of the eight settings shown below by setting the logic inputs of terminals DCNT0 through DCNT2.
Logic input DCNT1 0 0 0 0 1 1 1 1 DCNT2 0 0 1 1 0 0 1 1 DCNT0 0 1 0 1 0 1 0 1 Count BU9252S / F 256 512 768 1024 1280 1536 1792 2048 Delay time (ms) (when fOSC = 455kHz) BU9252S / F 18.00 36.01 54.01 72.02 90.02 108.03 126.03 144.04
5
Multimedia ICs
BU9252S / BU9252F
Maximum and minimum delay times when using 300kHz, 375kHz and 455kHz ceramic oscillators
Delay time (ms) 300kHz Max. 218.45 Min. 27.30 Max. 174.76 375kHz Min. 21.85 Max. 144.04 455kHz Min. 18.00
(4) Peripheral components of the ceramic oscillator An oscillator circuit can be configured simply by attaching a 455kHz ceramic resonator.
OSCI
Rf Rd OSCO
*External dimensions (Units: mm)
BU9252S
19.4 0.3 18 10 6.5 0.3 7.8 0.3 5.4 0.2 18
BU9252F
11.2 0.2 10
0.51Min.
3.95 0.3
1
9 7.62
1
0.3 0.1
9
1.8 0.1
3.4 0.2
0.11
1.27
0.4 0.1
0.3Min. 0.15
1.778
0.5 0.1
0 ~ 15
SDIP18
SOP18
6
0.15 0.1

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